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61108hkim/d1803si(ot) no.7307-1/18 http://onsemi.com semiconductor components industries, llc, 2013 june, 2013 stk672-070-e overview the stk672-070-e is a stepping motor driver hybrid ic that uses power mosfets in the output stage. it includes a built-in microstepping controller and is based on a uni polar constant-current pwm system. the stk672-070-e supports application simplification and standardization by providing a built-in 4 phase distribution stepping motor controller. it supports five excitation methods: 2 phase, 1-2 phase, w1-2 phase, 2w1-2 phase, and 4w1-2 phase excitations, and can provide control of the basic stepping angle of the stepping motor divided into 1/16 step units. it also allows the motor speed to be controlled with only a clock signal. the use of this hybrid ic allows designers to implement sy stems that provide high motor torques, low vibration levels, low noise, fast response, and high-efficiency drive. this product is provided in a smaller package than earlier stk672-040-e for easier mounting in end products. applications ? facsimile stepping motor drive (send and receive) ? paper feed and optical system stepping motor drive in copiers ? laser printer drum drive ? printer carriage stepping motor drive ? x-y plotter pen drive ? other stepping motor applications note*: conditions: v cc 1 = 24v, i oh = 1.5a, 2w1-2 excitation mode. ordering number : en7307b thick-film hybrid ic unipolar constant-c urrent chopper (external excitation pwm) circuit with built-in microstepping controller stepping motor driver (sine wave drive) output current 1.5a (no heat sink*)
stk672-070-e no.7307-2/18 features ? can implement stepping motor drive systems simply by providing a dc power supply and a clock pulse generator. ? one of five drive types can be selected with the drive mode settings (m1, m2, and m3) 1) 2 phase excitation drive 2) 1-2 phase excitation drive 3) w1-2 phase excitation drive 4) 2w1-2 phase excitation drive 5) 4w1-2 phase excitation drive ? phase retention even if excitation is switched. ? provides the moi phase origin monitor pin. ? the clk input counter block can be selected to be one of the following by the high/low setting of the m3 input pin. 1) rising edge only 2) both rising and falling edges ? the clk input pin includes built-in malfunction prevention circuits for external pulse noise. ? enable and reset pins provided. these ar e schmitt trigger inputs with built-in 20k (typical) pull-up resistors. ? no noise generation due to the differe nce between the a and b phase time cons tants during motor hold since external excitation is used. ? microstepping operation supported even for small motor curr ents, since the reference voltage vref can be set to any value between 0v and 1/2v cc 2. ? external excitation pwm drive allows a wide operating supply voltage range (v cc 1 = 10 to 45v) to be used. ? current detection resistor (0.22 ) built-in the hybrid ic itself. ? power mosfets adopted for low drive loss. ? provides a motor output drive current of i oh = 1.5a. (at tc = 105 c) specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc 1 max no signal 52 v maximum supply voltage 2 v cc 2 max no signal -0.3 to +7.0 v input voltage v in max logic input pins -0.3 to +7.0 v output current i oh max 0.5s, 1 pulse, with v cc 1 applied 2.0 a repeated avalanche capacity ear max 25 mj allowable power dissipation pd max c-a = 0 6.5 w operating ic substrate temperature tc max 105 c junction temperature tj max 150 c storage temperature tstg -40 to +125 c allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit supply voltage 1 v cc 1 with signals applied 10 to 45 v supply voltage 2 v cc 2 with signals applied 5 5% v input voltage v ih 0 to v cc 2v phase driver withstand voltage v dss tr1, 2, 3, and 4 (the a, a, b, and b outputs) 100 (min) v output current 1 i oh 1 tc = 105 c, clk 200hz 1.5 a output current 2 i oh 2 tc = 80 c, clk 200hz 1.7 a stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
stk672-070-e no.7307-3/18 electrical characteristics at tc = 25 c, v cc 1 = 24v, v cc 2 = 5v rating parameters symbols conditions min typ max unit control supply current i cc pin 6, with enable pin held low. 2.1 14 ma output saturation voltage vsat r l = 12 0.65 1.2 v average output current ioave load: r = 3.5 / l = 3.8mh for each phase 0.445 0.5 0.56 a fet diode forward voltage vdf if = 1a 1 1.8 v [control inputs] v ih except for the vref pin 4 v input voltage v il except for the vref pin 1 v i ih except for the vref pin 0 1 10 a input current i il except for the vref pin 125 250 510 a [vref input pin] input voltage v i pin 7 0 2.5 v input current i i pin 7, 2.5v input 330 415 545 a [control outputs] v oh i = ?3ma, pins moi 2.4 v output voltage v ol i = +3ma, pins moi 0.4 v [current distribution ratio (ab)] 2w1-2, w1-2, 1-2 vref = 1/8 100 % 2w1-2, w1-2 vref = 2/8 92 % 2w1-2 vref = 3/8 83 % 2w1-2, w1-2, 1-2 vref = 4/8 71 % 2w1-2 vref = 5/8 55 % 2w1-2, w1-2 vref = 6/8 40 % 2w1-2 vref = 7/8 21 % 2 vref 100 % pwm frequency fc 37 47 57 khz note: a constant-voltage power supply must be used. the design target value is shown for the current distribution ratio. package dimensions unit:mm (typ) 4186 1 15 46.6 41.2 12.7 25.5 (6.6) 14 2.0=28 3.6 0.5 2.0 8.5 4.0 0.4 2.9 1.0
stk672-070-e no.7307-4/18 internal block diagram 14 13 15 12 11 10 9 8 6 7 5 4 3 2 + + ? ? 1 m1 m2 cwb clock m3 reset moi enable sub pg bb b ab a vref v cc 2 phase advance counter pwm control reference clock generation a13256 excitation mode control excitation state monitor current distribution ratio switching pseudo-sine wave generator rc oscillator phase excitation drive signal generation rise/fall detection and switching
stk672-070-e no.7307-5/18 test circuit diagrams vsat vdf i ih , i il ioave, i cc , fc for ioave measurement: set switch sw1 to the b position, provide the vref input and switch over switch sw2. for fc measurement: set sw1 to the a position, set vref to 0v, and sw itch over switch sw3. for i cc measurement: set the enable input to the low level. 11 8 9 7 13 1 2 3 4 5 a rl ab b bb 6 + + v cc 2 v cc 2 stk672-070-e start v ref=2.5v v 1 2 3 4 5 a ab b bb 6 v cc 1 stk672-070-e v a a13257 11 8 9 7 13 1 2 3 4 5 a a b a b ab b sw2 sw3 sw1 bb 6 15 v cc 2 vref enable v cc 1 v cc 1 stk672-070-e start a13260 8 1 6 a a 2.5v v cc 2 m1 stk672-070-e a13259 a13258 9 m2 12 m3 11 clk 10 cwb 14 13 reset 15 enable 7 vref a a fc i il i ih
stk672-070-e no.7307-6/18 power-on reset the application must perform a power-on reset operation when v cc 2 power is first applied to this hybrid ic. application circuit that used 2w1-2 phase excitation (microstepping operation) mode. setting the motor current the motor current i oh is set by the vref voltage on the hybrid ic pin 7. the following formula gives the relationship between i oh and vref. rox = (ro2 6k ) (ro2 + 6k ) (1) vref = v cc 2 rox (ro1 + rox) (2) i oh = (3) k: 5.16 (voltage divider ratio), rs: 0.22 (this is the hybrid ic's internal current detection resistor. it has a tolerance of 3%.) applications can use motor currents from the current (0.05 to 0.1a) set by the duty of the frequency set by the oscillator up to the limit of the allowable operating range, i oh = 1.5a function table m2 0 0 1 1 m1 m3 0 1 0 1 phase switching clock edge timing 1 2 phase excitation 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation rising edge only 0 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation 4w1-2 phase excitation rising and falling edges forward reverse enable motor current is cut off when low cwb 0 1 reset active low k 1 rs vref motor current waveform ioave i ol i oh 0a a13262 7 5 a ab 6 14 14 8 14 14 9 14 14 12 15 11 13 10 14 + + v cc 2=5v v cc 2=5v sg 100 f or higher pg vref ro1 ro2 v cc 2=5v clk enable cbw reset moi v cc 1=10v to 45v two-phase stepping motor stk672-070-e a13261 b bb rox 4 3 2 1 v f 0.3v simple power on reset circuit (this circuit cannot be used for power supply voltage drop detection.) we recommend a value of about 100 for ro2 to minimize the influence of the vref pin internal impedance, which is 6k rox: input impedance: 6k ? 30%
stk672-070-e no.7307-7/18 functional description external excitation chopper drive block description driver block basic circuit structure since this hybrid ic adopts an external excitation method, no external oscillator circuit is required. when a high level is input to a in the basic driver block circuit shown in the figure and the mosfet is turned on, the comparator + input will go low and the comparator output will go low. since a set signal with the pwm period will be input, the q output will go high, and the mosf et will be turned on as its initial value. the current i on flowing in the mosfet passes through l1 and generates a potential difference in rs. then, when the rs potential and the vref potential become the same, the co mparator output will invert, and the reset signal q output will invert to the low level. then, the mosfet will be turned off and the energy stored in l1 will be induced in l2 and the current i off will be regenerated to the power supply. this state will be maintained until the time when an input to the latch circuit set pin occurs. in this manner, the q output is turned off and on repeatedly by the reset and set signals, thus implementing constant current control. the resistor and capacito r on the comparator input are spike re moval circuit elements and synchronize with the pwm frequency. since this hybrid ic uses a fixed frequency due to the external excitation method and at the same time also adopts a synchronized pwm technique, it ca n suppress the noise associated with holding a position when the motor is locked. input pin functions pin no. symbol function pin circuit type 11 clk phase switching clock built-in pull-up resistor cmos schmitt trigger input 10 cwb rotation direction setting (cw/ccw) built-in pull-up resistor cmos schmitt trigger input 15 enable output cutoff built-in pull-up resistor cmos schmitt trigger input 8, 9, 12 m1, m2, m3 excitation mode setting bu ilt-in pull-up resistor cmos schmitt trigger input 13 reset system reset built-in pull-up resistor cmos schmitt trigger input 7 vref current setting input impedance 6k (typ.) 30% a13263 d1 rs l2 v cc 1 i off l1 mosfet and q s r 800khz 45khz latch circuit noise filter cr oscillator divider current divider vref a=1 + ? enable a (control signal) i on
stk672-070-e no.7307-8/18 input signal functions and timing ? clk (phase switching clock) 1) input frequency range: dc to 50khz 2) minimum pulse width: 10 s 3) duty: 40 to 60% (however, the minimum pulse width takes precedence when m3 is high.) 4) pin circuit type: built-in pull-up resistor (20k , typical) cmos schmitt trigger structure 5) built-in multi-stage noise rejection circuit 6) function: - when m3 is high or open: the phase excited (driven) is advanced one step on each clk rising edge. - when m3 is low: the phase is advanced one step by both rising and falling edges, for a total of two steps per cycle. clk input acquisition timing (m3 = low) ? cwb (method for setting the rotation direction) 1) pin circuit type: built-in pull-up resistor (20k , typical) cmos schmitt trigger structure 2) function: - when cwb is low: the motor turns in the clockwise direction. - when cwb is high: the motor turns in the counterclockwise direction. 3) notes: when m3 is low, the cwb input must not be changed for about 6.25 s before or after a rising or falling edge on the clk input. ? enable (controls the on/off state of the a, a, b, and b excitation drive outputs and sel ects either operating or hold as the internal state of this hybrid ic.) 1) pin circuit type: built-in pull-up resistor (20k , typical) cmos schmitt trigger structure 2) function: - when enable is high or open: normal operating state - when enable is low: this hybrid ic goes to the hol d state and excitation drive output (motor current) is forcibly turned off. in this mode, the hybrid ic system clock is stopped and no inputs other than the reset input have any effect on the hybrid ic state. excitation counter up/down control output switching timing clk input system clock phase excitation counter cloc k control output timing a13264
stk672-070-e no.7307-9/18 ? m1, m2, and m3 (excitation mode and clk input edge timing selection) 1) pin circuit type: built-in pull-up resistor (20k , typical) cmos schmitt trigger structure 2) function: m2 0 0 1 1 m1 m3 0 1 0 1 phase switching clock edge timing 1 2 phase excitation 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation rising edge only 0 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation 4w1-2 phase excitation rising and falling edges 3) valid mode setting timing: applications must not change the mode in the period 5 s before or after a clk signal rising or falling edge. mode setting acquisition timing ? reset (resets all parts of the system.) 1) pin circuit type: built-in pull-up resistor (20k , typical) cmos schmitt trigger structure 2) function: - all circuit states are set to their initial values by settin g the reset pin low. (note that the pulse width must be at least 10 s.) at this time, the a and b phases are set to their origin , regardless of the excitation mode. the output current goes to about 71% after the reset is released. 3) notes: when power is first applied to this hybrid ic, vref must be established by applying a reset. applications must apply a power on reset when the v cc 2 power supply is first applied. ? vref (sets the current level used as the reference for constant-current detection.) 1) pin circuit type: analog input structure 2) function: - constant-current control can be applied to the motor excitation current at 100% of the rated current by applying a voltage less than the control system power supply voltage v cc 2 minus 2.5v. - applications can apply constant-current control proportiona l to the vref voltage, with this value of 2.5v as the upper limit. output pin functions pin no. symbol function pin circuit type 14 moi phase excitation origin monitor standard cmos structure output signal functions and timing ? a, a, b, and b (motor phase excitation outputs) 1) function: - in the 4 phase and 2 phase excitation modes, a 3.75 s (typical) interval is set up between the a and a and b and b output signal transition times. mode switching timing excitation counter up/down clk input system clock mode setting m1 to m3 mode switching clock hybrid ic internal setting state phase excitation clock a13265
stk672-070-e no.7307-10/18 phase states during excitation switching ? excitation phases before and after excita tion mode switching b24 24 27 28 31 3 4 5 8 11 12 15 16 19 20 25 a a a 0 16 17 1 a a b b b24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20 22 22 23 a a b b 8 9 12 4 28 20 20 24 28 0 4 8 12 16 b24 26 28 30 a a a 0 16 18 20 22 24 28 0 4 8 12 16 20 20 28 4 12 20 28 4 0 12 16 16 18 20 22 24 25 27 29 31 1 3 5 7 9 23 22 8 24 20 10 26 18 12 16 14 28 30 6 4 2 0 11 21 13 19 15 17 24 28 0 4 8 12 16 20 26 28 30 0 2 4 6 8 10 12 14 2 4 6 b b a b a b 30 2 26 6 10 14 22 18 a b a b a b a b b a a b b 8 10 12 14 12 4 28 20 2w1-2 phase 2 phase 2w1-2 phase 1-2 phase 2w1-2 phase w1-2 phase w1-2 phase 2 phase w1-2 phase 1-2 phase w1-2 phase 2w1-2 phase 1-2 phase 2 phase 1-2 phase w1-2 phase 1-2 phase 2w1-2 phase 2 phase 1-2 phase 2 phase w1-2 phase 2 phase 2w1-2 phase 24 0 8 16 20 22 30 28 4 12 20 14 28 4 12 a b a b 29 1 25 5 9 13 21 24 28 0 4 8 12 16 20 17 a b a b 29 5 4 12 20 6 13 21 28 17 a b a b excitation phase immediately before setting the excitation mode excitation phase according to the first clock input pulse after changing the excitation mode setting (m1 and m2) a1326 6
stk672-070-e no.7307-11/18 ? excitation phases before and after excitation mode switching b24 23 24 25 28 29 0 1 4 5 8 9 12 13 16 17 20 21 a a a 0 16 15 31 a a b b b24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20 22 22 23 a a b b 8 7 12 4 28 20 20 24 28 0 4 8 12 16 b24 30 a a a 0 16 22 24 28 0 4 8 12 16 20 20 28 4 12 16 28 24 20 0 4 12 16 18 20 22 24 25 27 29 31 1 3 5 7 9 23 22 8 24 20 10 26 18 12 16 14 28 30 6 4 2 0 11 21 13 19 15 17 24 28 0 4 8 12 16 20 26 28 30 0 2 4 6 8 10 12 14 6 b b a b a b 30 2 26 6 10 14 22 18 a b a b a b a b b a a b b 8 14 12 4 28 20 2w1-2 phase 2 phase 2w1-2 phase 1-2 phase 2w1-2 phase w1-2 phase w1-2 phase 2 phase w1-2 phase 1-2 phase w1-2 phase 2w1-2 phase 1-2 phase 2 phase 1-2 phase w1-2 phase 1-2 phase 2w1-2 phase 2 phase 1-2 phase 2 phase w1-2 phase 2 phase 2w1-2 phase 24 0 8 16 20 26 2 10 28 4 12 20 28 4 12 20 18 28 4 12 a b a b 30 3 27 7 11 15 23 24 28 0 4 8 12 16 20 19 a b a b 27 3 11 19 a b a b a13267
stk672-070-e no.7307-12/18 excitation time and timing charts ? clk rising edge operation m1 0 m2 0 m3 reset cwb clk moi 0 1 2 phase excitation timing chart (m3 = 1) m1 1 0 1 0 m2 0 m3 reset cwb clk moi 1-2 phase excitation timing chart (m3 = 1) m1 1 1 0 m2 0 m3 reset cwb clk moi 0 w1-2 phase excitation timing chart (m3 = 1) m1 1 0 1 0 1 0 m2 m3 reset cwb clk moi 2w1-2 phase excitation timing chart (m3 = 1) mosfet gate signal comparator reterence voltage a a b b vref a vref b 100% 71% 100% 71% comparator reterence voltage vref a 100% 92% 71% 40% vref b 100% 92% 71% 40% moi comparator reterence voltage vref a 100% 92% 83% 71% 55% 40% 20% moi mosfet gate signal a a b b mosfet gate signal comparator reterence voltage a a b b vref a vref b 100% 71% 100% 71% mosfet gate signal a a b b vref b 100% 92% 83% 71% 55% 40% 20% a13268
stk672-070-e no.7307-13/18 ? clk rising and falling edge operation m1 0 m2 0 m3 reset cwb clk mosfet gate signal comparator reterence voltage a a b b moi vref a vref b 100% 71% 100% 71% comparator reterence voltage vref a vref b 100% 92% 83% 71% 55% 40% 20% 20% 0 1-2 phase excitation timing chart (m3 = 0) m1 1 0 m2 0 m3 reset cwb clk 0 w1-2 phase excitation timing chart (m3 = 0) m1 0 m2 0 1 m3 reset cwb clk moi 100% 92% 83% 71% 55% 40% comparator reterence voltage vref a 100% 97% 88% 77% 66% 48% 31% 66% 48% 31% 14% 92% 83% 71% 55% 40% 20% 0 2w1-2 phase excitation timing chart (m3 = 0) m1 1 0 1 0 m2 0 m3 reset cwb clk moi 0 4w1-2 phase excitation timing chart (m3 = 0) mosfet gate signal a a b b mosfet gate signal comparator reterence voltage a a b b moi vref a vref b 100% 71% 40% 92% 100% 92% 71% 40% mosfet gate signal a a b b vref b 100% 97% 88% 77% 14% 92% 83% 71% 55% 40% 20% a13269
stk672-070-e no.7307-14/18 thermal design the main elements internal to this hybrid ic with la rge average power losses are the current control devices, the regenerative current diodes, and the current detection resistor. since sine wave drive is used, the average power loss during microstepping drive can be approximated by applying a waveform factor of 0.64 to the square wave loss during 2 phase excitation. the losses in the various excitation modes are as follows. 2 phase excitation pd 2ex = (vsat+vdf) i oh t2 + (vsat t1+vdf t3) 1-2 phase excitation pd 1-2ex = 0.64 {(vsat+vdf) i oh t2 + (vsat t1+vdf t3)} w1-2 phase excitation pd w1-2ex = 0.64 {(vsat+vdf) i oh t2 + (vsat t1+vdf t3)} 2w1-2 phase excitation pd 2w1-2ex = 0.64 {(vsat+vdf) i oh t2 + (vsat t1+vdf t3)} 4w1-2 phase excitation pd 4w1-2ex = 0.64 {(vsat+vdf) i oh t2 + (vsat t1+vdf t3)} here, t1 and t3 can be determined from the same formulas for all excitation methods. t1 = n (1 ? i oh ) t3 = n ( ) however, the formula for t2 differs with the excitation method. 2 phase excitation t2 = ? (t1+t3) 1-2 phase excitation t2 = ? t1 w1-2 phase excitation t2 = ? t1 2w1-2 phase excitation t2 = ? t1 4w1-2 phase excitation motor phase current model figure (2 phase excitation) fclock : clk input frequency (hz) vsat : the voltage drop of the power mosfet and the current detection resistor (v) vdf : the voltage drop of the body diode and the current detection resistor (v) i oh : phase current peak value (a) t1 : phase current rise time (s) v cc 1 : supply voltage applied to the motor (v) t2 : constant-current operating time (s) l : motor inductance (h) t3 : phase switching current regeneration time (s) r : motor winding resistance ( ) 2 fclock 2 fclock oh i 4 fclock 4 fclock oh i 8 fclock 8 fclock oh i 16 fclock 16 fclock oh i 16 fclock 16 fclock oh i 0.35 r l + ? 1 cc v 0.35 r + r l ? 0.35 1 cc v r oh i 0.35 1 cc v + + + fclock 2 fclock 3 fclock 7 fclock 15 t3 t1 t2 i oh a13270
stk672-070-e no.7307-15/18 determine c-a for the heat sink from the average power loss determined in the previous item. tc max: hybrid ic substrate temperature ( c) c-a = [ c/w] ta: application internal temperature ( c) pd ex : hybrid ic internal average loss (w) determine c-a from the above formula and then size s (in cm 2 ) of the heat sink from the graphs shown below. the ambient temperature of the device will vary greatly acco rding to the air flow conditions within the application. therefore, always verify that the size of the heat sink is adequate to assure that the hybrid ic back surface (the aluminum plate side) will never exceed a tc max of 105 c, whatever the operating conditions are. next we determine the usage conditions with no heat sink by determining the allowable hybrid ic internal average loss from the thermal resistan ce of the hybrid ic subs trate, namely 25.5c/w. for a tc max of 105c at an ambient temperature of 50c pd ex = = 2.15w for a tc max of 105c at an ambient temperature of 40c pd ex = = 2.54w this hybrid ic can be used with no heat sink as long as it is used at operating conditions below the losses listed above. (see tc ? pd curve in the graph on page 17.) the junction temperature, tj, of each device can be determin ed from the loss pds in each transistor and the thermal resistance j-c. tj = tc + j-c pds (c) here, we determine pds, the loss for each transistor, by determining pd ex in each excitation mode. pds = pd ex /4 the steady-state thermal resistance j-c of a power mosfet is 19.2 c/w. ex pd ta - max tc 25.5 50 - 100 25.5 40 - 100 ic internal average power loss, pd - w c-a - pd heat sink thermal resistance, c-a - c/w heat sink surface area, s - cm 2 c-a - s heat sink thermal resistance, c-a - c/w 4 0 8 12 16 20 0246810121416 4 0 c 6 0 c g u a r a n t e e d a m b i e n t t e m p e r a t u r e c-a= tc max -- ta (c/w) tc max=105c pd no. fin 25.5 (c/w) 5 0 c 2 1.0 3 7 5 10 2 10 23 57 100 23 5 no. fin 25.5 (c/w) 2 m m a l p l a t e ( n o s u r f a c e f i n i s h ) ( f l a t b l a c k s u r f a c e f i n i s h ) vertical standing type natural convection air cooling
stk672-070-e no.7307-16/18 50 100 200 300 400 450 150 250 350 0 0 0.5 1.0 1.5 2.0 2.5 3.0 0 20406080100120 10 15 20 25 30 35 40 45 50 0.2 0.4 0.8 1.2 1.6 0.6 1.0 1.4 0 0.2 0.4 0.8 1.2 0.6 1.0 1.4 0 0.2 0.4 0.8 1.2 1.6 0.6 1.0 1.4 1.8 0 0 0.5 1.5 2.5 1.0 2.0 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 35 39 43 47 51 55 37 41 45 49 53 0 20406080100120 4.0 4.4 4.8 5.2 5.6 6.0 4.2 4.6 5.0 5.4 5.8 vsat - i oh motor current, i oh - a output saturation voltage, vsat - v vdf - i oh motor current, i oh - a internal diode forward voltage, vdf - v itf02185 itf02186 fc - v cc 2 supply voltage, v cc 2 - v pwm frequency, fc - khz fc - tc substrate temperature, tc - c pwm frequency, fc - khz itf02183 itf02184 35 39 43 47 51 55 37 41 45 49 53 i oh -tc substrate temperature, tc - c motor current, i oh - a itf02187 itf02188 t c = 1 0 5 c 2 5 c tc = 2 5 c 1 0 5 c test motor: pk244-01b test motor: pk244-01b 0 20406080100120 50 100 200 300 400 450 150 250 350 0 ivref - tc substrate temperature, tc - c reference voltage input current, ivref - a itf02189 itf02190 vref=2.0v vref=1.5v vref=1.0v vref=0.5v i oh - v cc 1 motor current, i oh - a motor supply voltage, v cc 1 - v ivref - vref reference voltage, vref - v reference voltage input current, ivref - a
stk672-070-e no.7307-17/18 notes ? the current ranges shown above apply when the ou tput voltage is not in the avalanche range. ? the operating substrate temperature tc values shown above are measured during motor operation. since tc varies with the ambient temperat ure ta, the value of i oh , and whether i oh is continuous or intermittent, it must be measured in an actual operating system. 0.5 1.0 2.0 1.5 2.5 5 10 20 30 40 15 25 35 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 10 20 40 60 30 50 70 80 90 0.2 0.4 0.8 1.2 1.6 1.8 2.0 0.6 1.0 1.4 0 10000 1000 23 57 100 23 57 100000 23 57 10 15 20 25 30 35 40 45 50 0 0 vref - i oh motor current, i oh - v reference voltage, vref - v tc - pd hybrid ic internal average power dissipation, pd - w substrate temperature increase, tc - c itf02191 itf02192 test motor: pk244-01b v cc 1=24v test motor: pk264-01b v cc 1=24v, v cc 2=5v i oh =1a (with no heat sink) 0 20406080100120 0 substrate temperature rise test clk frequency, pps - hz substrate temprature increase, tc - c motor current i oh derating vs. operating substrate temperature tc. substrate temprature, tc - c motor current, i oh - a itf02193 itf02194 2 e x 4 w 1 - 2 e x
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